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The need to relieve throughput bottlenecks in computing and communications has caused the move to high speed serial buses. While 5.0 GT/s PCI Express® (PCIe®) is aimed at improving throughput for graphics or memory intensive applications such as interfacing video cards in computing, 5 GT/s is also favored over 2.5 GT/s as fewer lanes, but at higher speed, often reduce the cost of the Add-In card. Because the PCIe serial data rates of 2.5 GT/s and 5.0 GT/s are in the microwave range, they require significant attention to signal integrity for successful compliance testing.

Testing can be done at two levels: the Base Specification, or the Card Electro-Mechanical (CEM) level, a subset of the full base specification used for compliance workshops. This document describes testing to verify receiver compliance with the PCI Express Card Electro-Mechanical (CEM) Specification Revision 2.0 and highlights four important areas in receiver compliance testing:

• Jitter generator requirements including jitter spectrum
• Use of 4-tap de-emphasis to obtain specified voltages at compliance point
• How rise time filters makes the test signal follow the mask optimally
• Compliance Base Board configuration requirements which still allow toggling for transmitter compliance tests