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The need to relieve throughput bottlenecks in computing and communications, together with the development of low cost, high speed CMOS technology, has caused the move to high speed serial buses.  PCI Express® (PCIe®) is aimed at replacing PCI for applications such as interfacing video cards in computing.  Because the PCIe serial data rates of 2.5 GT/s and 5.0 GT/s are in the microwave range, they require significant attention to signal integrity for successful compliance testing.  Testing can be done at two levels:  the Base Specification; or the Card Electro-Mechanical (CEM) level, a subset of the full base specification used for compliance workshops.  This document describes testing to verify receiver compliance with the PCI Express Base Specifications Revision 2.0[i] and highlights three important areas in receiver compliance testing:

• Jitter generator requirements including clock recovery
• Calibration channel requirements
• Compliance baseboard configuration requirement